Semiconductor memory devices may be divided into volatile semiconductor memory devices, such as a dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, and non-volatile semiconductor memory devices, such as read only memory (ROM) devices, flash memory devices or electrically erasable and programmable read only memory (EEPROM) devices. In a flash memory device, data may be electrically stored into the flash memory device or read out from the flash memory device using a Fowler-Nordheim tunneling method or a channel hot electron injection method.
A method of manufacturing a non-volatile semiconductor memory device such as the flash memory device is disclosed in U.S. Pat. No. 6,465,293 issued to Park et al. As described in the Park et al. Abstract, the method comprises the steps of forming an oxide film on a semiconductor substrate in which a device separation film is formed and then patterning the oxide film to expose the semiconductor substrate at a portion in which a floating gate will be formed; sequentially forming a tunnel oxide film and a first polysilicon layer on the entire structure, and then flattening the first polysilicon layer until the tunnel oxide film is exposed to form a floating gate; etching the tunnel oxide film and the oxide film in the exposed portion to a given thickness and the forming a dielectric film on the entire structure; sequentially forming a second polysilicon layer, a tungsten silicide layer and a hard mask and then patterning them to form a control gate; and injecting impurity ions into the semiconductor substrate at the both sides of the floating gate to form a junction region.
As the integration density of semiconductor devices continues to increase, an opening defined by an oxide pattern that partially exposes a semiconductor substrate may have a high aspect ratio. When the opening has the high aspect ratio, a polysilicon layer filling up the opening may have a void therein in a process for manufacturing the semiconductor device.
FIG. 1 is an electron microscopic photograph illustrating a void generated in a polysilicon layer in a conventional method for forming a floating gate.
As shown in FIG. 1, a void 12 generated in a polysilicon layer 10 may not be removed in a planarization process for forming the floating gate. Thus, a portion of the floating gate around the void 12 may be oxidized in successive processes, thereby deteriorating electrical characteristics of a semiconductor device including the floating gate.